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Students can begin to lose interest in CS as early as 2nd grade, indicating the importance of engaging students in CS as early as possible. This study examined the integration of computational thinking (CT) into literacy activities in early childhood education (K-2). We describe the co-design process of developing computational thinking literacy integrated curriculum for K-2, and preliminary results of K-2 student engagement in CT and literacy activities 

Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS₂, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe₂transistors with impressive subthreshold slope (109 mV dec⁻¹) andI_ON/I_OFF(10⁶) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe₂in situbefore metallization, which minimizes subsequent reactions between Sc and WSe₂. Post metallization anneals in reducing environments (UHV, forming gas) degrade theI_ON/I_OFFby ~10³and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe₂, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe₂layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe₂Fermi level around individual Sc atoms in the WSe₂lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe₂transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe₂.

 

The transfer‐free direct growth of high‐performance materials and devices can enable transformative new technologies. Here, room‐temperature field‐effect hole mobilities as high as 707 cm²V⁻¹s⁻¹are reported, achieved using transfer‐free, low‐temperature (≤120 °C) direct growth of helical tellurium (Te) nanostructure devices on SiO₂/Si. The Te nanostructures exhibit significantly higher device performance than other low‐temperature grown semiconductors, and it is demonstrated that through careful control of the growth process, high‐performance Te can be grown on other technologically relevant substrates including flexible plastics like polyethylene terephthalate and graphene in addition to amorphous oxides like SiO₂/Si and HfO₂. The morphology of the Te films can be tailored by the growth temperature, and different carrier scattering mechanisms are identified for films with different morphologies. The transfer‐free direct growth of high‐mobility Te devices can enable major technological breakthroughs, as the low‐temperature growth and fabrication is compatible with the severe thermal budget constraints of emerging applications. For example, vertical integration of novel devices atop a silicon complementary metal oxide semiconductor platform (thermal budget <450 °C) has been theoretically shown to provide a 10× systems level performance improvement, while flexible and wearable electronics (thermal budget <200 °C) can revolutionize defense and medical applications.